The present invention relates to an amplifier circuit unit for amplifying a burst signal, in particular, for use in an optical receiving circuit, and an amplifier circuit comprising plural amplifier circuit units.
In an optical digital communication system, an optical receiving circuit for amplifying an attenuated signal is indispensable. This optical receiving circuit is required to have functions for converting an optical signal into a current signal by a photo diode, further converting this current signal into a voltage signal, and amplifying to an amplitude of voltage so as to be distinguished logically.
A conventional optical receiving circuit is composed as shown in a block diagram in FIG. 16, in which an optical signal h .nu. is converted into a current signal Iin by a photo detector PD (photo diode), and this current signal Iin is put into a pre-amplifier circuit 3. This pre-amplifier circuit 3 converts the current signal Iin into a voltage signal t. The voltage signal t is passed through a capacitor C to be rid of low frequency components, and becomes a voltage signal u, which is fed into an amplitude limiting amplifier circuit 41 of a main amplifier circuit 4. The amplitude limiting amplifier circuit 41 receives a fixed voltage v from a voltage source E as a threshold, and amplifies the voltage signal u, and issues a pulse signal data row w that can be distinguished logically.
That is, in the conventional amplifier circuit, cutting off the low frequency components of the input signal, the DC level was made constant regardless of the input signal level, and the fixed threshold was used as the reference for amplifying the signal voltage by the amplitude limiting amplifier circuit 41.
Recently, an optical communication system using a burst mode digital data signal is being studied, and high speed response when starting data input is required in the optical receiving circuit.
In such prior art, however, high speed response upon start of data input and same code continuity tolerance cannot be satisfied at the same time.
FIG. 17A shows an input signal waveform (a) into the amplitude limiting amplifier circuit 41 when starting data input in the case of setting the capacitor C at small value and low band cut-off frequency at high value in FIG. 16, and FIG. 17B is an explanatory diagram of relation of output data waveform (b). FIG. 19A shows an input signal waveform (a) into the amplitude limiting amplifier circuit 41 when starting data input in the case of setting the capacitor C at large value and low band cut-off frequency at low value in FIG. 16, and FIG. 19B is an explanatory diagram of output data waveform (b). In FIG. 17A and FIG. 19A, in order that .phi. level may be issued in the no-signal input period, it is set so that the potential v may be lower than potential u at the time of no-signal input.
Comparing these waveforms, it is known that by setting the low band cut-off frequency at higher value, the DC level fluctuations are faster, the intermediate level of input data u can be brought closer to the fixed threshold level v in a shorter time, and the distortion and deterioration period upon data input start can be shortened.
FIG. 18A shows an input signal waveform (a) into the amplitude limiting amplifier circuit 41 in single continuity mode in the case of setting the capacitor C at small value and low band cut-off frequency at large value in FIG. 16, and FIG. 18B is a diagram showing an output data waveform (b). By contrast, FIG. 20A shows an input signal waveform (a) into the amplitude limiting amplifier circuit 41 in single continuity mode in the case of setting the capacitor C at large value and low band cut-off frequency at low value in FIG. 16, and FIG. 20B is an explanatory diagram of an output data waveform (b). In FIG. 18A and FIG. 20A, in order that .phi. level may be issued in the no-signal input period, it is set so that the potential v may be lower than potential u at the time of no-signal input.
In FIG. 18A, since the DC level fluctuations are fast, as shown in FIG. 18B, the logic of the output data is inverted in single continuity mode, whereas in FIG. 20A, DC level fluctuations are slow, it is known to have a high tolerance to same code continuity (FIG. 20B).
As explained herein, in the prior art, when the low band cut-off frequency is set higher, a high speed response characteristic is obtained upon start of data input, but, to the contrary, the same code continuity tolerance is lowered. Opposite to the above conditions, when the low band cut-off frequency is set lower, the same code continuity tolerance is enhanced but the high speed response characteristic upon start of data input is sacrificed, and such trade-off relation exists.